[Verilog] Modules and Ports

Modules

A module is a basic building block consisting of distinct parts.

module name, port list, port declarations, optional parameters …

• SR Latch Example

module SR_latch(Q, Qbar, R, Rbar);
output Q, Qbar;
input R, Rbar;

nand n1(Q, Sbar, Qbar);
nand n2(Qbar, Q, Rbar);

endmodule

 

List of Ports

Ports(terminal) provide the interface by which a module can communictaion with its environment.
⇒ the environment can interact with the module only through its ports

• 4-bit Full Adder Exampleoutput : sum, c_outTop : instantiated

  module fulladd4(sum, c_out, a, b, c_in);
  
  output [3:0] sum;
  output c_out;
  
  intput [3:0] a, b;
  input c_in;
  
  endmodule
  
  module Top
  	reg [3:0] A, B;
  	reg C_IN;
  	reg [3:0] SUM;
  	wire C_OUT;
  
  	fulladd4 fa0(SUM, C_OUT, A, B, C_IN);
  
  endmodule
  

  
  fulladd4 : full adder module
  input : a, b, c_in

Port Connection Rules

• Input
  Externally : reg, net
  Internally : net
• Outputs
  Externally : net ( no reg type )
  Interally : reg, net
• Inouts : net

 

• Width Matching
  internal and external port bit widths should match when making intermodule port connections, otherwise, a warning is issued.
• Unconnected Ports
  출력 안하려고 비워두기 가능 ⇒ warning
  Verilog allows ports to remain unconnected for certain reasons.

Connecting Ports

• connecting by ordered list
  자리에 맞추어서 parameter를 하나씩 매핑
• connecting ports by name (Named mapping)

fulladd4 fa_byname(.sum(SUM), .b(B), .c_in(C_IN), .a(A),);

Hierarchical Names

a hierarchical name is a list of identifiers separated by dots for each level of hierarchy
=> %m을 이용해서 확인할 수 있다.