[Verilog] Hierarchical Modeling Concepts

Design Methodology (설계 방법론)

• Top-down
• Define top-level → Identify sub-blocks → leaf cells
• Bottom-up
• Identify building blocks → build bigger cells → top-level

Ripple Carry Counter Design

1. 4-bit Ripple Carry Counter
   : 0000 → 0001 → 0010 → 0011 → 0100 → … → 1111 → 0000

2.  Negative edge-triggered toggle flip-flop (T-FF) based counter

• Top-down design methodologyBuild the T-FFs form the D-FF and an inverter
• implement the counter with T-FFs
• Bottom-up design methodologyDesign T-FF & Ripple Carry Counter
• → 우리가 실습에서 사용한 방법
• Build D-FF from AND & OR gates

 

Modules

: basic building blocks
providing the necessary functionality to the higher-level block
( similar with function / class in C/C++)

module <module_name> (<module_terminal_list>);

endmodule

Four Levels of Abstraction

• Behavioral or algorithmic level
• Dataflow level
• Gate level
• Switch level